The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and relates, for example, to both an eDRAM in which a DRAM and a logic circuit are mounted mixedly, and a manufacturing method thereof.
A DRAM in an eDRAM (Embedded Dynamic Random Access Memory) has, for example: a plurality of word lines each extending in a first direction of a main surface of a semiconductor substrate; a plurality of bit lines each extending in a second direction that intersects with the first direction; and a plurality of DRAM cells each of which is arranged in a portion where the word line and the bit line intersect with each other and electrically coupled to the word line and the bit line.
The DRAM cell includes one selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and one capacitive element coupled in series to the selection MISFET. The selection MISFET includes both a gate electrode formed integrally with the word line and a semiconductor region serving as a source and a drain, and one of the source and the drain (e.g., source) is electrically coupled to the bit line, while the other (e.g., drain) is electrically coupled to the capacitive element.
The DRAM includes: a CUB (Capacitor Under Bit line) type in which the capacitive element is arranged in a layer under the bit line; and a COB (Capacitor Over Bit line) type in which the capacitive element is arranged in a layer over the bit line. Generally, the COB type is more advantageous in terms of high integration of a DRAM and miniaturization of a chip.
An example of the COB type DRAM is disclosed, for example, in Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2002-353334). In this DRAM, the selection MISFET is covered with a first insulating film, and a first plug electrode is formed in a first contact hole formed in the first insulating film so as to expose the source and the drain of the selection MISFET, and the first plug electrode is coupled to each of the source and the drain of the selection MISFET. The bit line and a cap insulating film over the bit line are embedded in a second insulating film formed over the first insulating film, and the bit line is coupled to the source of the selection MISFET via the first plug electrode. A third insulating film is arranged over the second insulating film, and a capacitive element is formed in the third insulating film. The cap insulating film is arranged over the bit line, so that the capacitive element and the bit line are insulated from each other. A second contact hole is formed in the second insulating film so as to expose the first plug electrode coupled to the drain of the selection MISFET, and a second plug electrode is formed in the second contact hole. The capacitive element is coupled to the drain of the selection MISFET via the first plug electrode and the second plug electrode that are arranged in a laminated state.
Another example of the COB type DRAM is disclosed in Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2011-49250). In this DRAM, a selection MISFET is covered with a first insulating film; a bit line contact hole and a wiring trench that communicates with the bit line contact hole are formed in the first insulating film; and a bit line contact is formed in the bit line contact hole and the wiring trench such that the bit line contact is coupled to the source of the selection MISFET. A first contact hole is formed in the first insulating film, and a first contact plug is formed in the first contact hole such that the first contact plug is coupled to the drain of the selection MISFET. A second insulating film and a third insulating film are formed over the first insulating film, and a capacitive element is formed in the third insulating film. The capacitive element and the bit line contact are isolated from each other by the second insulating film, and the capacitive element is coupled to the first contact plug via an opening formed in the second insulating film.